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? semiconductor components industries, llc, 2013 january, 2013 ? rev. 6 1 publication order number: ncp3020/d ncp3020a, ncp3020b, NCV3020A, ncv3020b synchronous pwm controller the ncp3020 is a pwm device designed to operate from a wide input range and is capable of producing an output voltage as low as 0.6 v. the ncp3020 provides integrated gate drivers and an internally set 300 khz (ncp3020a) or 600 khz (ncp3020b) oscillator. the ncp3020 also has an externally compensated transconductance error amplifier with an internally fixed soft ? start. protection features include lossless current limit and short circuit protection, output overvoltage protection, output undervoltage protection, and input undervoltage lockout. the ncp3020 is currently available in a soic ? 8 package. features ? input voltage range from 4.7 v to 28 v ? 300 khz operation (ncp3020b ? 600 khz) ? 0.6 v internal reference voltage ? internally programmed 6.8 ms soft ? start (ncp3020b ? 4.4 ms) ? current limit and short circuit protection ? transconductance amplifier with external compensation ? input undervoltage lockout ? output overvoltage and undervoltage detection ? ncv prefix for automotive and other applications requiring site and change controls ? this is a pb ? free device figure 1. typical application circuit comp fb vcc bst hsdr vsw lsdr gnd q1 q2 vout c c1 c c2 c in r iset r c c bst r fb1 r fb2 c 0 l 0 v in http://onsemi.com device package shipping ? ordering information ncp3020adr2g soic ? 8 (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. soic ? 8 nb case 751 marking diagram 3020x alyw 1 8 3020x = specific device code x = a or b a = assembly location l = wafer lot y = year w = work week = pb ? free package 1 8 pin connections lsdr gnd vsw fb hsdr comp bst v cc ncp3020bdr2g soic ? 8 (pb ? free) 2500 / tape & reel NCV3020Adr2g soic ? 8 (pb ? free) 2500 / tape & reel ncv3020bdr2g soic ? 8 (pb ? free) 2500 / tape & reel
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 2 gate drive logic vc clk/ dmax/ soft start oov boost clamp level shift sample & hold vc hsdr lsdr gnd ? + ? + ? + vcc comp fb ref ramp oscillator bst vsw vcc figure 2. ncp3020 block diagram internal bias iset 1.5 v bst_chrg thermal sd por/startup ota pwm comp ouv current limit pin function description pin pin name description 1 v cc the v cc pin is the main voltage supply input. it is also used in conjunction with the vsw pin to sense current in the high side mosfet. 2 comp the comp pin connects to the output of the operational transconductance amplifier (ota) and the positive terminal of the pwm comparator. this pin is used in conjunction with the fb pin to compensate the voltage mode control feedback loop. 3 fb the fb pin is connected to the inverting input of the ota. this pin is used in conjunction with the comp pin to compensate the voltage mode control feedback loop. 4 gnd ground pin 5 lsdr the lsdr pin is connected to the output of the low side driver which connects to the gate of the low side n ? fet. it is also used to set the threshold of the current limit circuit (i set ) by connecting a resistor from lsdr to gnd. 6 vsw the vsw pin is the return path for the high side driver. it is also used in conjunction with the v cc pin to sense current in the high side mosfet. 7 hsdr the hsdr pin is connected to the output of the high side driver which connects to the gate of the high side n ? fet. 8 bst the bst pin is the supply rail for the gate drivers. a capacitor must be connected between this pin and the vsw pin.
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 3 absolute maximum ratings (measured vs. gnd pin 8, unless otherwise noted) rating symbol v max v min unit high side drive boost pin bst 45 ? 0.3 v boost to v sw differential voltage bst ? v sw 13.2 ? 0.3 v comp comp 5.5 ? 0.3 v feedback fb 5.5 ? 0.3 v high ? side driver output hsdr 40 ? 0.3 v low ? side driver output lsdr 13.2 ? 0.3 v main supply voltage input v cc 40 ? 0.3 v switch node voltage v sw 40 ? 0.6 v maximum average current v cc , bst, hsdrv, lsdrv, v sw , gnd i max 130 ma operating junction temperature range (note 1) t j ? 40 to +140 c maximum junction temperature t j(max) +150 c storage temperature range t stg ? 55 to +150 c thermal characteristics (note 2) soic ? 8 plastic package thermal resistance junction ? to ? air r ja 165 c/w lead temperature soldering (10 sec): reflow (smd styles only) pb ? free (note 3) r f 260 peak c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. the maximum package power dissipation limit must not be exceeded. p d t j(max) t a r ja 2. when mounted on minimum recommended fr ? 4 or g ? 10 board 3. 60 ? 180 seconds minimum above 237 c.
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 4 electrical characteristics ( ? 40 c < t j < +125 c, v cc = 12 v, for min/max values unless otherwise noted) characteristic conditions min typ max unit input voltage range ? 4.7 28 v supply current v cc supply current ncp3020a v fb = 0.55 v, switching, v cc = 4.7 v ? 5.5 8.0 ma v fb = 0.55 v, switching, v cc = 28 v ? 7.0 11 ma v cc supply current ncp3020b v fb = 0.55 v, switching, v cc = 4.7 v ? 5.9 10 ma v fb = 0.55 v, switching, v cc = 28 v ? 7.8 13 ma under voltage lockout uvlo rising threshold v cc rising edge 4.0 4.3 4.7 v uvlo falling threshold v cc falling edge 3.5 3.9 4.3 v oscillator oscillator frequency ncp3020a t j = +25 c, 4.7 v v cc 28 v 250 300 350 khz t j = ? 40 c to +125 c, 4.7 v v cc 28 v 240 300 360 khz oscillator frequency ncp3020b t j = +25 c, 4.7 v v cc 28 v 550 600 650 khz t j = ? 40 c to +125 c, 4.7 v v cc 28 v 530 600 670 khz ramp ? amplitude voltage v peak ? v alley (note 4) ? 1.5 ? v ramp valley voltage 0.46 0.70 0.88 v pwm minimum duty cycle (note 4) ? 7.0 ? % maximum duty cycle ncp3020a ncp3020b 80 75 84 80 ? ? % soft start ramp time ncp3020a ncp3020b v fb = v comp ? ? 6.8 4.4 ? ? ms error amplifier (gm) transconductance 0.9 1.4 1.9 ms open loop dc gain (notes 4 and 6) ? 70 ? db output source current v fb = 545 mv 45 75 100 a output sink current v fb = 655 mv 45 75 100 a fb input bias current ? 0.5 500 na feedback voltage t j = 25 c 4.7 v < v cc < v in < 28 v, ? 40 c < t j < +125 c 0.591 0.588 0.6 0.6 0.609 0.612 v v comp high voltage v fb = 0.55 v 4.0 4.4 5.0 v comp low voltage v fb = 0.65 v ? 72 250 mv output voltage faults feedback oov threshold 0.66 0.75 0.84 v feedback ouv threshold 0.42 0.45 0.48 v overcurrent iset source current 7.0 13 18 a current limit set voltage (note 5) t j = 25 c, r set = 22.5 k 140 240 360 mv 4. guaranteed by design. 5. the voltage sensed across the high side mosfet during conduction. 6. this assumes 100 pf capacitance to ground on the comp pin and a typical internal r o of > 10 m . 7. this is not a protection feature.
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 5 electrical characteristics ( ? 40 c < t j < +125 c, v cc = 12 v, for min/max values unless otherwise noted) characteristic unit max typ min conditions gate drivers and boost clamp hsdrv pullup resistance t j = 25 c, v cc = 8 v, v bst = 7.5 v, v sw = gnd 100 ma out of hsdr pin 5.0 11 20 hsdrv pulldown resistance t j = 25 c, v cc = 8 v, v bst = 7.5 v, v sw = gnd 100 ma into hsdr pin 2.0 5.0 11.5 lsdrv pullup resistance t j = 25 c, v cc = 8 v, v bst = 7.5 v, v sw = gnd 100 ma out of lsdr pin 5.0 9.0 16 lsdrv pulldown resistance t j = 25 c, v cc = 8 v, v bst = 7.5 v, v sw = gnd 100 ma into lsdr pin 1.0 3.0 6.0 hsdrv falling to lsdrv rising delay v in = 12 v, v sw = gnd, v comp = 1.3 v 50 80 110 ns lsdrv falling to hsdrv rising delay v in = 12 v, v sw = gnd, v comp = 1.3 v 60 80 120 ns boost clamp voltage v in = 12 v, v sw = gnd, v comp = 1.3 v 5.5 7.5 9.6 v thermal shutdown thermal shutdown (notes 4 and 7) ? 165 ? c hysteresis (notes 4 and 7) ? 20 ? c 4. guaranteed by design. 5. the voltage sensed across the high side mosfet during conduction. 6. this assumes 100 pf capacitance to ground on the comp pin and a typical internal r o of > 10 m . 7. this is not a protection feature.
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 6 typical performance characteristics figure 3. efficiency vs. output current and input voltage figure 4. load regulation vs. input voltage figure 5. switching waveforms (v in = 9 v) figure 6. switching waveforms (v in = 18 v) figure 7. feedback reference voltage vs. input voltage and temperature figure 8. switching frequency vs. input voltage and temperature (ncp3020a) i out (a) 10 6 4 2 0 60 65 70 75 80 85 90 95 efficiency (%) 8 i out (a) 10 6 4 2 0 3.25 3.255 3.26 3.265 3.27 3.275 3.28 v out (v) 8 temperature ( c) 125 110 50 5 ? 40 594 596 598 600 602 604 606 v fb (mv) v cc = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 temperature ( c) 125 110 50 5 ? 40 260 270 280 290 300 310 320 f sw (khz) v cc = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 330 340 v cc = 5 v 18 v 15 v 12 v 9 v 18 v 15 v 12 v 9 v v cc = 5 v typical application circuit figure 37 typical application circuit figure 37 ncp3020a input = 9 v, output = 3.3 v, load = 10 a c4 (green) = v in , c2 (red) = v out c1 (yellow) = vsw, c3 (blue) = hsdr input = 18 v, output = 3.3 v, load = 10 a c4 (green) = v in , c2 (red) = v out c1 (yellow) = vsw, c3 (blue) = hsdr
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 7 typical performance characteristics figure 9. switching frequency vs. input voltage and temperature (ncp3020b) figure 10. transconductance vs. input voltage and temperature figure 11. input undervoltage lockout vs. temperature figure 12. output overvoltage and undervoltage vs. input voltage and temperature figure 13. supply current vs. input voltage and temperature (ncp3020a) figure 14. supply current vs. input voltage and temperature (ncp3020b) temperature ( c) 125 110 50 5 ? 40 540 560 580 600 620 640 660 f sw (khz) v cc = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 v cc = 5 v temperature ( c) 125 110 50 5 ? 40 1.00 1.05 1.10 1.15 1.20 1.25 1.30 gm (ms) v cc = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 v cc = 5 v 1.35 1.40 1.45 1.50 temperature ( c) 125 110 50 5 ? 40 3.8 3.9 4.0 4.1 4.2 4.3 4.4 uvlo (v) uvlo rising ? 25 ? 10 20 35 65 80 95 temperature ( c) 125 110 50 5 ? 40 400 440 480 520 560 600 640 threshold voltage (mv) ? 25 ? 10 20 35 65 80 95 680 720 760 800 uvlo falling oov, v cc = 5 ? 28 v ouv, v cc = 5 ? 28 v temperature ( c) 125 110 50 5 ? 40 4.0 4.5 5.0 5.5 6.0 6.5 7.5 i cc , switching (ma) v cc = 28 v ? 25 ? 10 20 35 65 80 95 7.0 v cc = 12 v v cc = 5 v ncp3020a ncp3020b temperature ( c) 125 110 50 5 ? 40 5.0 5.5 6.0 6.5 7.0 7.5 9.0 i cc , switching (ma) ? 25 ? 10 20 35 65 80 95 8.0 8.5 v cc = 28 v v cc = 4.7 v ncp3020b
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 8 typical performance characteristics figure 15. ramp valley voltage vs. input voltage and temperature figure 16. soft ? start time vs. input voltage and temperature figure 17. current limit set current vs. temperature figure 18. soft ? start waveforms figure 19. shutdown waveforms figure 20. startup into a current limit temperature ( c) 125 110 50 5 ? 40 400 450 500 550 600 650 700 valley voltage (mv) ? 25 ? 10 20 35 65 80 95 750 800 850 900 v cc = 5 ? 28 v 950 1000 temperature ( c) 125 110 50 5 ? 40 5.0 5.5 6.0 6.5 7.0 7.5 8.0 ncp3020a t soft ? start (ms) v cc = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 v cc = 5 v temperature ( c) 125 110 50 5 ? 40 13 13.2 13.4 13.6 13.8 14 i set ( a) v cc = 12 v, 28 v ? 25 ? 10 20 35 65 80 95 v cc = 5 v ncp3020b t soft ? start (ms) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 v cc = 12 v, 28 v v cc = 5 v input = 12 v, output = 3.3 v, load = 5 a c1 (yellow) = v in , c4 (green) = v out c2 (red) = hsdr, c3 (blue) = lsdr input = 12 v, output = 3.3 v, load = 5 a c1 (yellow) = v in , c4 (green) = v out c2 (red) = hsdr, c3 (blue) = lsdr input = 12 v c1 (yellow) = fb, c3 (blue) = lsdr c2 (red) = hsdr, c4 (green) = v in ncp3020a ncp3020b
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 9 detailed description overview the ncp3020a/b operates as a 300/600 khz, voltage mode, pulse width modulated, (pwm) synchronous buck converter. it drives high ? side and low ? side n ? channel power mosfets. the ncp3020 incorporates an internal boost circuit consisting of a boost clamp and boost diode to provide supply voltage for the high side mosfet gate driver. the ncp3020 also integrates several protection features including input undervoltage lockout (uvlo), output undervoltage (ouv), output overvoltage (oov), adjustable high ? side current limit (i set and i lim ), and thermal shutdown (tsd). the operational transconductance amplifier (ota) provides a high gain error signal from vout which is compared to the internal 1.5 v pk-pk ramp signal to set the duty cycle converter using the pwm comparator. the high side switch is turned on by the positive edge of the clock cycle going into the pwm comparator and flip flop following a non-overlap time. the high side switch is turned off when the pwm comparator output is tripped by the modulator ramp signal reaching a threshold level established by the error amplifier. the gate driver stage incorporates fixed non ? overlap time between the high ? side and low ? side mosfet gate drives to prevent cross conduction of the power mosfet?s. por and uvlo the device contains an internal power on reset (por) and input undervoltage lockout (uvlo) that inhibits the internal logic and the output stage from operating until v cc reaches its respective predefined voltage levels (4.3 v typical). startup and shutdown once v cc crosses the uvlo rising threshold the device begins its startup process. closed ? loop soft ? start begins after a 400 s delay wherein the boost capacitor is charged, and the current limit threshold is set. during the 400 s delay the ota output is set to just below the valley voltage of the internal ramp. this is done to reduce delays and to ensure a consistent pre ? soft ? start condition. the device increases the internal reference from 0 v to 0.6 v in 24 discrete steps while maintaining closed loop regulation at each step. each step contains 64 switching cycles. some overshoot may be evident at the start of each step depending on the voltage loop phase margin and bandwidth. the total soft ? start time is 6.8 ms for the ncp3020a and 4.4 ms for the ncp3020b. figure 21. soft ? start details internal reference voltage 0 v 0.7 v ota output internal ramp 24 voltage steps 25 mv steps 0.6 v
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 10 oov and ouv the output voltage of the buck converter is monitored at the feedback pin of the output power stage. two comparators are placed on the feedback node of the ota to monitor the operating window of the feedback voltage as shown in figures 22 and 23. all comparator outputs are ignored during the soft ? start sequence as soft ? start is regulated by the ota and false trips would be generated. after the soft ? start period has ended, if the feedback is below the reference voltage of comparator 2 (v fb < 0.45 v), the output is considered ?undervoltage? and the device will initiate a restart. when the feedback pin voltage rises between the reference voltages of comparator 1 and comparator 2 (0.45 < v fb < 0.75), then the output voltage is considered ?power good.? finally , if the feedback voltage is greater than comparator 1 (v fb > 0.75 v), the output voltage is considered ?overvoltage,? and the device will latch off. to clear a latch fault, input voltage must be recycled. graphical representation of the oov and ouv is shown in figures 24 and 25. vref = 0.6 v vref*75% vref*125% comparator 1 comparator 2 logic soft start complete restart latch off fb figure 22. oov and ouv circuit diagram power good = 1 power good = 1 vref = 0.6 v voov = vref * 125% ouvp & power good = 0 oovp & power good = 0 hysteresis = 5 mv hysteresis = 5 mv power not good high power not good low figure 23. oov and ouv window diagram vouv = vref * 75%
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 11 0.6 v (vref *100%) 0.45 v (vref *75%) 0.75 v (vref *125%) fb voltage latch off reinitiate softstart softstart complete figure 24. powerup sequence and overvoltage latch 0.6 v (vref *100%) 0.45 v (vref * 75%) 0.75 v (vref *125%) fb voltage latch off reinitiate softstart softstart complete figure 25. powerup sequence and undervoltage soft ? start
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 12 current limit and current limit set overview the ncp3020 uses the voltage drop across the high side mosfet during the on time to sense inductor current. the i limit block consists of a voltage comparator circuit which compares the dif ferential voltage across the v cc pin and the v sw pin with a resistor settable voltage reference. the sense portion of the circuit is only active while the hs mosfet is turned on. control vset 6 rset iset 13 ua dac / counter ilim out hsdr lsdr vsw vin vcc itrip ref vsense switch cap figure 26. i set / i limit block diagram itrip ref ? 63 steps, 6.51 mv/step current limit set the i limit comparator reference is set during the startup sequence by forcing a typically 13 a current through the low side gate drive resistor. the gate drive output will rise to a voltage level shown in the equation below: v set i set *r set (eq. 1) where i set is 13 a and r set is the gate to source resistor on the low side mosfet. this resistor is normally installed to prevent mosfet leakage from causing unwanted turn on of the low side mosfet. in this case, the resistor is also used to set the i limit trip level reference through the i limit dac. the i set process takes approximately 350 s to complete prior to soft ? start stepping. the scaled voltage level across the i set resistor is converted to a 6 bit digital value and stored as the trip value. the binary i limit value is scaled and converted to the analog i limit reference voltage through a dac counter. the dac has 63 steps in 6.51 mv increments equating to a maximum sense voltage of 403 mv. during the i set period prior to soft ? start, the dac counter increments the reference on the i set comparator until it crosses the v set voltage and holds the dac reference output to that count value. this voltage is translated to the i limit comparator during the i sense portion of the switching cycle through the switch cap circuit. see figure 26. exceeding the maximum sense voltage results in no current limit. steps 0 to 10 result in an effective current limit of 0 mv. current sense cycle figure 27 shows how the current is sampled as it relates to the switching cycle. current level 1 in figure 27 represents a condition that will not cause a fault. current level 2 represents a condition that will cause a fault. the sense circuit is allowed to operate below the 3/4 point of a given switching cycle. a given switching cycle?s 3/4 t on time is defined by the prior cycle?s t on and is quantized in 10 ns steps. a fault occurs if the sensed mosfet voltage exceeds the dac reference within the 3/4 time window of the switching cycle.
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 13 1/4 1/2 to n ? 1 1/4 3/4 to n ? to n ? 2 ? to n ? 1 no trip: vsense < i trip ref at 3/4 point trip: vsense > i trip ref at 3/4 point 3/4 3/4 point determined by prior cycle vsense 1/2 current level 2 current level 1 itrip ref figure 27. i limit trip point description each switching cycle?s ton is counted in 10 ns time steps. the 3/4 sample time value is held and used for the following cycle?s limit sample time soft ? start current limit during soft ? start the i set value is doubled to allow for inrush current to charge the output capacitance. the dac reference is set back to its normal value after soft ? start has completed. v sw ringing the i limit block can lose accuracy if there is excessive v sw voltage ringing that extends beyond the 1/2 point of the high ? side transistor on ? time. proper snubber design and keeping the ratio of ripple current and load current in the 10 ? 30% range can help alleviate this as well. current limit a current limit trip results in completion of one switching cycle and subsequently half of another cycle t on to account for negative inductor current that might have caused negative potentials on the output. subsequently the power mosfets are both turned off and a 4 soft ? start time period wait passes before another soft ? start cycle is attempted. i ave vs trip point the average load trip current versus r set value is shown the equation below: i avetrip i set r set r ds(on) 1 4 v in v out l v out v in 1 f sw (eq. 2) where: l = inductance (h) i set = 13 a r set = gate to source resistance ( ) r ds(on) = on resistance of the hs mosfet ( ) v in = input voltage (v) v out = output voltage (v) f sw = switching frequency (hz) boost clamp functionality the boost circuit requires an external capacitor connected between the bst and v sw pins to store char ge for supplying the high and low ? side gate driver voltage. this clamp circuit limits the driver voltage to typically 7.5 v when v in > 9 v, otherwise this internal regulator is in dropout and typically v in ? 1.25 v. the boost circuit regulates the gate driver output voltage and acts as a switching diode. a simplified diagram of the boost circuit is shown in figure 28. while the switch node is grounded, the sampling circuit samples the voltage at the boost pin, and regulates the boost capacitor voltage. the sampling circuit stores the boost voltage while the v sw is high and the linear regulator output transistor is reversed biased. vin 8.9 v bst vsw lsdr figure 28. boost circuit switch sampling circuit
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 14 reduced sampling time occurs at high duty cycles where the low side mosfet is of f for the majority of the switching period. reduced sampling time causes errors in the regulated voltage on the boost pin. high duty cycle / input voltage induced sampling errors can result in increased boost ripple voltage or higher than desired dc boost voltage. figure 29 outlines all operating regions. the recommended operating conditions are shown in region 1 (green) where a 0.1 f, 25 v ceramic capacitor can be placed on the boost pin without causing damage to the device or mosfets. larger boost ripple voltage occurring over several switching cycles is shown in region 2 (y ellow). the boost ripple frequency is dependent on the output capacitance selected. the ripple voltage will not damage the device or 12 v gate rated mosfets. conditions where maximum boost ripple voltage could damage the device or 12 v gate rated mosfets can be seen in region 3 (orange). placing a boost capacitor that is no greater than 10x the input capacitance of the high side mosfet on the boost pin limits the maximum boost voltage < 12 v. the typical drive waveforms for regions 1, 2 and 3 (green, yellow, and orange) regions of figure 29 are shown in figure 30. region 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 2 11 . 5v region 2 22v region 3 4 6 8 10 12 14 16 18 20 22 24 26 28 duty cycle input voltage normal operation increased boost ripple (still in specification) increased boost ripple capacitor optimization required 71% maxi mum duty cycle boost voltage levels max duty cycle figure 29. safe operating area for boost voltage with a 0.1 f capacitor
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 15 vboost vin 7.5v normal maximum vboost vin normal maximum 0v vboost vin 7.5v figure 30. typical waveforms for region 1 (top), region 2 (middle), and region 3 (bottom) 7.5v 7.5v 7.5v 0v 7.5v 0v to illustrate, a 0.1 f boost capacitor operating at > 80% duty cycle and > 22.5 v input voltage will exceed the specifications for the driver supply voltage. see figure 31.
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 16 boost voltage 0 2 4 6 8 10 12 14 16 18 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 24.5 26.5 input voltage (v) boost voltage (v) figure 31. boost voltage at 80% duty cycle voltage ripple maximum allowable voltage maximum boost voltage inductor selection when selecting the inductor, it is important to know the input and output requirements. some example conditions are listed below to assist in the process. table 1. design parameters design parameter example value input voltage (v in ) 9 v to 18 v nominal input voltage (v in ) 12 v output voltage (v out ) 3.3 v input ripple voltage (vin ripple ) 300 mv output ripple voltage (vout ripple ) 50 mv output current rating (i out ) 10 a operating frequency (fsw) 300 khz a buck converter produces input voltage (v in ) pulses that are lc filtered to produce a lower dc output voltage (v out ). the output voltage can be changed by modifying the on time relative to the switching period (t) or switching frequency. the ratio of high side switch on time to the switching period is called duty cycle (d). duty cycle can also be calculated using v out , v in , the low side switch voltage drop v lsd , and the high side switch voltage drop v hsd . f 1 t (eq. 3) d t on t ( d t off t (eq. 4) d v out
v lsd v in v hsd
v lsd d v out v in (eq. 5) 27.5% 3.3 v 12 v the ratio of ripple current to maximum output current simplifies the equations used for inductor selection. the formula for this is given in equation 6. ra i i out (eq. 6) the designer should employ a rule of thumb where the percentage of ripple current in the inductor lies between 10% and 40%. when using ceramic output capacitors the ripple current can be greater thus a user might select a higher ripple current, but when using electrolytic capacitors a lower ripple current will result in lower output ripple. now, acceptable values of inductance for a design can be calculated using equation 7. l v out i out ra f sw ( 1 d ) 3.3 h (eq. 7) 3.3 v 10 a 24% 300 khz ( 1 27.5% ) the relationship between ra and l for this design example is shown in figure 32.
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 17 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 10% 15% 20% 25% 30% 35% 40% v in , (v) l, inductance ( h) 18 v v out = 3.3 v 15 v 12 v 9 v figure 32. ripple current ratio vs. inductance to keep within the bounds of the parts maximum rating, calculate the rms current and peak current. i rms i out 1
ra 2 12 10.02 a (eq. 8) 10 a 1
(0.24) 2 12 i pk i out 1
ra 2 11.2 a 10 a 1
(0.24) 2 (eq. 9) an inductor for this example would be around 3.3 h and should support an rms current of 10.02 a and a peak current of 11.2 a. the final selection of an output inductor has both mechanical and electrical considerations. from a mechanical perspective, smaller inductor values generally correspond to smaller physical size. since the inductor is often one of the lar gest components in the regulation system, a minimum inductor value is particularly important in space ? constrained applications. from an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by equation 10. slewrate lout v in v out l out 2.6 a s (eq. 10) 12 v 3.3 v 3.3 h this equation implies that larger inductor values limit the regulator?s ability to slew current through the output inductor in response to output load transients. consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. this results in larger values of output capacitance to maintain tight output voltage regulation. in contrast, smaller values of inductance increase the regulator?s maximum achievable slew rate and decrease the necessary capacitance, at the expense of higher ripple current. the peak ? to ? peak ripple current for the ncp3020a is given by the following equation: i pp v out ( 1 d ) l out f sw (eq. 11) ipp is the peak to peak current of the inductor. from this equation it is clear that the ripple current increases as l out decreases, emphasizing the trade ? off between dynamic response and ripple current. the power dissipation of an inductor consists of both copper and core losses. the copper losses can be further categorized into dc losses and ac losses. a good first order approximation of the inductor losses can be made using the dc resistance as they usually contribute to 90% of the losses of the inductor shown below: lp cu i rms 2 dcr (eq. 12) the core losses and ac copper losses will depend on the geometry of the selected core, core material, and wire used. most vendors will provide the appropriate information to make accurate calculations of the power dissipation then the total inductor losses can be capture buy the equation below: lp tot lp cu_dc
lp cu_ac
lp core (eq. 13) input capacitor selection the input capacitor has to sustain the ripple current produced during the on time of the upper mosfet, so it must have a low esr to minimize the losses. the rms value of this ripple is: iin rms i out d ( 1 d ) (eq. 14) d is the duty cycle, iin rms is the input rms current, and i out is the load current. the equation reaches its maximum value with d = 0.5. loss in the input capacitors can be calculated with the following equation: p cin esr cin i in rms 2 (eq. 15) p cin is the power loss in the input capacitors and esr cin is the effective series resistance of the input capacitance. due to large di/dt through the input capacitors, electrolytic or ceramics should be used. if a tantalum must be used, it must by surge protected. otherwise, capacitor failure could occur. input start ? up current to calculate the input startup current, the following equation can be used. i inrush c out v out t ss (eq. 16) i inrush is the input current during startup, c out is the total output capacitance, v out is the desired output voltage, and t ss is the soft start interval. if the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used.
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 18 output capacitor selection the important factors to consider when selecting an output capacitor is dc voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. the output capacitor must be rated to handle the ripple current at full load with proper derating. the rms ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies but a multiplier is usually given for higher frequency operation. the rms current for the output capacitor can be calculated below: co rms i o ra 12 (eq. 17) the maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the equivalent series inductance (esl) and esr. the main component of the ripple voltage is usually due to the esr of the output capacitor and the capacitance selected. v esr_c i o ra esr co
1 8 f sw co (eq. 18) the esl of capacitors depends on the technology chosen but tends to range from 1 nh to 20 nh where ceramic capacitors have the lowest inductance and electrolytic capacitors then to have the highest. the calculated contributing voltage ripple from esl is shown for the switch on and switch off below: v eslon esl i pp f sw d (eq. 19) v esloff esl i pp f sw ( 1 d ) (eq. 20) the output capacitor is a basic component for the fast response of the power supply. in fact, during load transient, for the first few microseconds it supplies the current to the load. the controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. during a load step transient the output voltage initially drops due to the current variation inside the capacitor and the esr (neglecting the effect of the effective series inductance (esl)). v out ? esr i tran esr co (eq. 21) a minimum capacitor value is required to sustain the current during the load transient without discharging it. the voltage drop due to output capacitor discharge is approximated by the following equation: v out ? dischg i tran 2 l out c out v in v out (eq. 22) in a typical converter design, the esr of the output capacitor bank dominates the transient response. it should be noted that vout ? discharge and vout ? esr are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the esl). conversely during a load release, the output voltage can increase as the energy stored in the inductor dumps into the output capacitor. the esr contribution from equation 18 still applies in addition to the output capacitor charge which is approximated by the following equation: v out ? chg i tran 2 l out c out v out (eq. 23) power mosfet selection power dissipation, package size, and the thermal environment drive mosfet selection. to adequately select the correct mosfets, the design must first predict its power dissipation. once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature. power dissipation has two primary contributors: conduction losses and switching losses. the control or high ? side mosfet will display both switching and conduction losses. the synchronous or low ? side mosfet will exhibit only conduction losses because it switches into nearly zero voltage. however, the body diode in the synchronous mosfet will suffer diode losses during the non ? overlap time of the gate drivers. starting with the high ? side or control mosfet, the power dissipation can be approximated from: p d_control p cond
p sw_tot (eq. 24) the first term is the conduction loss of the high ? side mosfet while it is on. p cond i rms_control 2 r ds(on)_control (eq. 25) using the ra term from equation 6, i rms becomes: i rms_control i out d 1
ra 2 12 (eq. 26) the second term from equation 24 is the total switching loss and can be approximated from the following equations. p sw_tot p sw
p ds
p rr (eq. 27) the first term for total switching losses from equation 27 includes the losses associated with turning the control mosfet on and off and the corresponding overlap in drain voltage and current. p sw p ton
p toff (eq. 28) 1 2 i out v in f sw t on
t off
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 19 where: t on q gd i g1 q gd v bst v th r hspu
r g (eq. 29) and: t off q gd i g2 q gd v bst v th r hspd
r g (eq. 30) next, the mosfet output capacitance losses are caused by both the control and synchronous mosfet but are dissipated only in the control mosfet. p ds 1 2 q oss v in f sw (eq. 31) finally the loss due to the reverse recovery time of the body diode in the synchronous mosfet is shown as follows: p rr q rr v in f sw (eq. 32) the low ? side or synchronous mosfet turns on into zero volts so switching losses are negligible. its power dissipation only consists of conduction loss due to r ds(on) and body diode loss during the non ? overlap periods. p d_sync p cond
p body (eq. 33) conduction loss in the low ? side or synchronous mosfet is described as follows: p cond i rms_sync 2 r ds(on)_sync (eq. 34) where: (eq. 35) i rms_sync i out ( 1 d ) 1
ra 2 12 the body diode losses can be approximated as: p body v fd i out f sw nol lh
nol hl (eq. 36) vth figure 33. mosfet switching characteristics i g1 : output current from the high ? side gate drive (hsdr) i g2 : output current from the low ? side gate drive (lsdr) ? sw : switching frequency of the converter. ncp3020a is 300 khz and ncp3020b is 600 khz v bst : gate drive voltage for the high ? side drive, typically 7.5 v. q gd : gate charge plateau region, commonly specified in the mosfet datasheet v th : gate ? to ? source voltage at the gate charge plateau region q oss : mosfet output gate charge specified in the data sheet q rr : reverse recovery charge of the low ? side or synchronous mosfet, specified in the datasheet r ds(on)_control : on resistance of the high ? side, or control, mosfet r ds(on)_sync : on resistance of the low ? side, or synchronous, mosfet nol lh : dead time between the lsdr turning off and the hsdr turning on, typically 85 ns nol hl : dead time between the hsdr turning off and the lsdr turning on, typically 75 ns once the mosfet power dissipations are determined, the designer can calculate the required thermal impedance for each device to maintain a specified junction temperature at the worst case ambient temperature. the formula for calculating the junction temperature with the package in free air is: t j t a
p d r ja t j : junction temperature t a : ambient temperature p d : power dissipation of the mosfet under analysis r ja : thermal resistance junction ? to ? ambient of the mosfet?s package as with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e. worst case mosfet r ds(on) ).
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 20 figure 34. mosfets timing diagram high ? side logic signal low ? side logic signal high ? side mosfet low ? side mosfet r dsmax r ds(on)min r dsmax r ds(on)min nol hl nol lh t f t d(on) t r t d(off) t r t f t d(on) t d(off) another consideration during mosfet selection is their delay times. turn ? on and turn ? off times must be short enough to prevent cross conduction. if not, there will be conduction from the input through both mosfets to ground. therefore, the following conditions must be met. t d(on)_control
nol lh t d(off)_sync
t f _sync (eq. 37) t (on)_sync
nol hl t d(off)_control
t f _control and the mosfet parameters, t d(on) , t r , t d(off) and t f are can be found in their appropriate datasheets for specific conditions. nol lh and nol hl are the dead times which were described earlier and are 85 ns and 75 ns, respectively. feedback and compensation the ncp3020 is a voltage mode buck convertor with a transconductance error amplifier compensated by an external compensation network. compensation is needed to achieve accurate output voltage regulation and fast transient response. the goal of the compensation circuit is to provide a loop gain function with the highest crossing frequency and adequate phase margin (minimally 45 ). the transfer function of the power stage (the output lc filter) is a double pole system. the resonance frequency of this filter is expressed as follows: f p0 1 2 l c out (eq. 38) parasitic equivalent series resistance (esr) of the output filter capacitor introduces a high frequency zero to the filter network. its value can be calculated by using the following equation: f z0 1 2 c out esr (eq. 39) the main loop zero crossover frequency f 0 can be chosen to be 1/10 ? 1/5 of the switching frequency. table 2 shows the three methods of compensation. table 2. compensation types zero crossover frequency condition compensation type typical output capacitor type f p0 < f z0 < f 0 < f s /2 type ii electrolytic, tantalum f p0 < f 0 < f z0 < f s /2 type iii method i tantalum, ceramic f p0 < f 0 < f s /2 < f z0 type iii method ii ceramic
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 21 compensation type ii this compensation is suitable for electrolytic capacitors. components of the type ii (figure 35) network can be specified by the following equations: figure 35. type ii compensation r c1 2 f 0 l v ramp v out esr v in v ref gm (eq. 40) c c1 1 0.75 2 f p0 r c1 (eq. 41) c c2 1 r c1 f s (eq. 42) r1 v out v ref v ref r2 (eq. 43) v ramp is the peak ? to ? peak voltage of the oscillator ramp and gm is the transconductance error amplifier gain. capacitor c c2 is optional. compensation type iii tantalum and ceramics capacitors have lower esr than electrolytic, so the zero of the output lc filter goes to a higher frequency above the zero crossover frequency. this requires a type iii compensation network as shown in figure 36. there are two methods to select the zeros and poles of this compensation network. method i is ideal for tantalum output capacitors, which have a higher esr than ceramic: figure 36. type iii compensation f z1 0.75 f p0 (eq. 44) f z2 f p0 (eq. 45) f p2 f z0 (eq. 46) f p3 f s 2 (eq. 47) method ii is better suited for ceramic capacitors that typically have the lowest esr available: f z2 f 0 1 sin max 1
sin max (eq. 48) f p2 f 0 1
sin max 1 sin max (eq. 49) f z1 0.5 f z2 (eq. 50) f p3 0.5 f s (eq. 51) max is the desired maximum phase margin at the zero crossover frequency, ? 0 . it should be 45 ? 75 . convert degrees to radians by the formula: max max degress 2 360 :units radians (eq. 52) the remaining calculations are the same for both methods. r c1 2 gm (eq. 53) c c1 1 2 f z1 r c1 (eq. 54) c c2 1 2 f p3 r c1 (eq. 55) c fb1 2 f 0 l v ramp c out v in r c1 (eq. 56) r fb1 1 2 c fb1 f p2 (eq. 57) r1 1 2 c fb1 f z2 r fb1 (eq. 58) r2 v ref v out v ref r1 (eq. 59) if the equation in equation 60 is not true, then a higher value of r c1 must be selected. r1 r2 r fb1 r1 r fb1
r2 r fb1
r1 r2 1 gm (eq. 60)
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 22 typical application circuit 9 ? 18 v vcc bst hsdr vsw lsdr comp fb 3.3 v c bst q2 q1 3.3 uh r iset r fb1 c out ? 2/3 c c1 r c c c2 gnd r fb2 c in ? 1/2 r gs r fb3 c fb d1 c in ? 3/4 c in ? 5 c out ? 1 r g ncp3020a figure 37. typical application, v in = 9 ? 18 v, v out = 3.3 v, i out = 10 a reference designator value cin ? 1 470 f cin ? 2 470 f cin ? 3 22 f cin ? 4 22 f cin ? 5 1 f cc1 33 pf cc2 8.2 nf cfb 1.8 nf cout1 470 f cout2 22 f cout3 22 f cbst 0.1 f rc 4.75 k rg 8.06 rgs 1.0 k riset 22.1 k rfb1 4.53 k rfb2 1.0 k rfb3 2.49 k q1 ntmfs4841n q2 ntmfs4935 d1 bat54
ncp3020a, ncp3020b, NCV3020A, ncv3020b http://onsemi.com 23 package dimensions soic ? 8 nb case 751 ? 07 issue ak seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp3020/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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